In a TDM (time division multiplexed) data transmission system, it is not particularly important that the system be able to quickly recover a clock signal embodied in received data. In these systems, data is continuously received at what is essentially a constant level and with a constant phase. Consequently, once the appropriate level and phase are identified, they are not likely to change very often. When they do change, even if the level and phase are recovered (i.e. the receiver synchronizes itself with the data) very slowly (e.g., 100 microseconds), the time required to do so is still very small in comparison to the time which was spent transmitting data between resynchronization events (e.g., an hour or a day). Thus, the efficiency of the system will remain relatively high even if the system is very slow to synchronize itself.
In a packet switched system, on the other hand, it is very important to minimize the time required to synchronize the receiver with the data. This is because each successive packet of data which is received may originate from a different source node. Successive packets may therefore be out of phase of each other and may have different signal levels. In order to be able to correctly identify the data in a given packet, it is necessary for the receiver to synchronize itself with that packet. Because the receiver must be synchronized with each successive packet, the synchronization must take much less time than in a TDM system in order to maintain a high efficiency. For instance, if the time it takes to transmit the data in each packet is 1 microsecond, the receiver must be able to synchronize itself with each packet in 50 nanoseconds in order to maintain an efficiency of 95%. Moreover, if it takes too long to synchronize the receiver with the packet, the data in the packet may actually be lost.
Because packet switching systems are in such widespread use, many attempts have been made to identify faster means for rapidly recovering clock signals from data packets. Several approaches are conventionally used to provide the fastest means for locking in a phase locked loop (PLL). These approaches can be characterized as falling into either of two categories: zero acquisition time phase recovery PLL approaches; and traditional open loop PLL approaches.
Zero acquisition time phase recovery approaches are all based on a similar principle—discrete phase correlation. One problem with these approaches is that there are no existing devices using discrete phase correlation PLL architectures that operate at rates higher than 10 Gbps (gigabits per second). Another problem with these architectures is that they typically cannot distinguish between a 0 degree phase shift and a 180 degree phase shift. As a result, they may cause the system to stabilize out of phase or, in a more optimistic case, take a very long time to stabilize in phase. This problem can be illustrated by the example below.
Referring to FIG. 1, a block diagram illustrating a semi-classic PLL circuit is shown. This circuit uses a double-loop PLL architecture. An external second-order loop functions like an ordinary PLL circuit. An internal first-order loop functions as a phase alignment loop. The internal first-order loop functions essentially as described in the following paragraph.
Phase detector 11 provides a pulse indicating whether the phase of the voltage control oscillator (VCO) 12 precedes or follows the phase of the data transition on the incoming signal. Scalar amplifier 13 converts the pulse to a voltage level of constant magnitude v0. The voltage will be either positive or negative, depending upon whether the VCO phase leads or lags the data transition. If the voltage is positive, the VCO phase will shift one direction, and if it is negative, the VCO phase will shift the other direction. The VCO clock is thereby phase shifted by a fixed amount per clock cycle (or bit). This shifting of the VCO clock will continue until its phase is aligned with the incoming signal to a resolution equal to the magnitude of the phase shift per clock cycle. (It should be noted that this procedure may “overshoot” exact alignment of the clock signals, but will do so by no more than the amount of the phase shift per clock cycle.)
The problem with this system is, as noted above, that signals which are 180 degrees out of phase may look the same to the system as signals which are in phase. For example, an Alexander phase detector samples the incoming data signal at both rising and falling edges of the VCO clock signal. As shown in FIG. 2, shifting the VCO clock signal will cause the data signal to be sampled at exactly the same points. Thus, 180 degrees looks just like 0 degrees and the system may therefore remain at 180 degrees because the two signals appear to already be aligned.
While this may not always cause these systems to remain out of phase, it will typically cause the systems to take a substantially greater amount of time to align the phases of the signals. For example, it has been found that a MTC1234 CDR chip has a window of approximately 30 degrees (around 180 degrees) from which it is substantially slower to align the phases of the signals. It has been empirically determined that, within this window, this chip needs at least 200 ns to align the signals, while only 20 ns are needed outside this window.